library ieee;
use ieee.std_logic_1164.all;

entity counterBlock is
	port (
		en, clr, clk: in bit;
		output : out bit
	);
end entity counterBlock;

architecture STRUCTURAL of counterBlock is
	
	component counterModule
	
	port(input, en, clr, clk: in bit;
		output : out bit
	);
	
	end component; 
	
	component and3
	
	port(a,b,c : in bit;
		z : out bit
	);
	
	end component; 
	
	component or2
	
	port(a,b : in bit;
		z : out bit
	);
	
	end component;
	
		
	for all : counterModule use entity work.counterModule;
	for all : or2 use entity work.or2;
	for all : and3 use entity work.and3;
	
	signal sigVec : bit_vector(8 downTo 0);
	signal input: bit := '1';
	
	
begin

	COUNTER0 : counterModule  port map(input, en, clr, clk, sigVec(0));
	COUNTER1 : counterModule  port map(sigVec(0), en, clr, clk, sigVec(1));
	COUNTER2 : counterModule  port map(sigVec(1), en, clr, clk, sigVec(2));
	COUNTER3 : counterModule  port map(sigVec(2), en, clr, clk, sigVec(3));
	COUNTER4 : counterModule  port map(sigVec(3), en, clr, clk, sigVec(4));
	COUNTER5 : counterModule  port map(sigVec(4), en, clr, clk, sigVec(5));

	AND0 : and3  port map(sigVec(0), sigVec(1), sigVec(2), sigVec(6));
	AND1 : and3  port map(sigVec(3), sigVec(4), sigVec(5), sigVec(7));
	
	OR0 : or2 port map(sigVec(6), sigVec(7), sigVec(8)); 
	
	
	
	output <= sigVec(3);

end STRUCTURAL;